The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing OFF-state current, and reducing short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. However, such advanced devices also present new challenges. Indeed, one of the most pressing existing challenges is the reduction of source/drain contact resistance. In at least some examples, increased source/drain doping is used in an attempt to reduce contact resistance. However, source/drain ion implantation doping can result in dopant tailing, even when a pre-amorphization implant (PAI) is used, which can cause threshold voltage shift or other short-channel effects. For example, boron doping of PMOS source/drain regions may result in doping tailing and threshold voltage shift. For NMOS source/drain regions, which may be doped for example with phosphorous or arsenic, the benefits of reduced source/drain resistance by increased doping have been limited for instance by: (i) maximum dopant concentration achievable, (ii) NMOS dopant participation in subsequent silicide (e.g., TiSi) reaction/formation, and (iii) heavily doped source/drain induced short-channel effects.
Thus, existing techniques have not proved entirely satisfactory in all respects.